In the figure, there is data flow to the ADC ( a, b, c, d, e, f, g, …) and a circular buffer initially containing a, b, c, and d. 14.7 gives a simple illustration of the 2-bit circular buffer. The circular buffer acts like a first-in/first-out (FIFO) buffer, but each datum on the buffer does not have to be moved.
If the sum of the M register content and the I register content crosses the buffer boundary, the modified I register value is calculated by the modulus logic using the L register value. Each time an I register is selected, the corresponding L register provides the modulus logic with the length information. L registers and I registers are paired and the selection of the L register (L0-3 in DAG1, L4-7 in DAG2) is determined by the I register used. For linear addressing, the modulus logic is disabled by setting the corresponding L register to 0. For circular buffer addressing, the L register is initialized with the length of the buffer. The value of the L register determines which addressing scheme is used. The address generators support both linear and circular addressing. The modification values stored in the M register are signed numbers so that the next address can be either higher or lower. In other words, any register in the 10-3 set may be modified by any register in the M0-3 set in any combination but not by those in DAG2 (M4-7). The choice of the I and M registers is independent within each DAG.
After an indirect data access, the specified M register (M0-3 in DAG2) is added to the specified I register to generate the new I value.
#Alternate mac address generator generator#
The data address generator employs a postmodification scheme. (Reproduced by permission of Analog Devices, Inc.)
Block diagram of the ADSP-2101’s data address generator.
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